1. Field of Invention
The present invention relates to a semiconductor device and an operating method thereof. More specifically, the present invention relates to a read operation of a semiconductor device.
2. Description of Related Art
Semiconductor devices generally include a memory cell array for storing data.
The memory cell array includes a plurality of memory blocks. In NAND flash type memory, the memory blocks include a plurality of cell strings connected between bit lines and a source line. For example, each cell string includes a source select transistor, a plurality of memory cells and a drain select transistor connected in series between the bit line and the source line.
In a read operation (or, a verification operation) of the semiconductor device, bit lines are precharged, and a source line is grounded. At this time, a read voltage is applied to a selected word line and it is determined, based on variation in potentials of the bit lines whether, selected memory cells are programmed.
Because the source line is commonly connected to the plurality of cell strings, the potential of the source line may be temporarily increased in the read operation by a variety of complex causes, such as degradation of the source line or current flowing in the cell string, etc. The above-mentioned phenomenon is called source bouncing.
In particular, when source bouncing occurs during a read operation, the threshold voltage of the selected memory cells may be higher than the read voltage, although the threshold voltage of the selected memory cells should be lower than the read voltage. That is, the threshold voltage of the memory cells may be higher than the actual threshold voltage thereof. Thus, the reliability of read operations may be degraded.
Therefore, research for decreasing source bouncing has been actively studied. However, source bouncing has not been eliminated.